BUILD
RELIABLE
PRODUCTS
with
RELIABLE
SERVICES
Navigate left to find out more
about AMIQ Consulting
Visit Website
Since the company inception in 2003, we have helped customers overcome resource and time constraints and accomplish their hardware verification goals.
Our team of consultants can develop and deploy in-house verification flows, from standard methodology customization through infrastructure implementation down to post-deployment tracking. See more
We provide ASIC and FPGA functional verification services spanning the entire verification flow from module to system level. Our consultants are proficient in the e language and SystemVerilog, as well as in methodologies like eRM, UVM, OVM, VMM. See more
We have experience in developing VIP on demand for any protocol or function, using the e language, SystemVerilog, or SystemC. See more
Our most experienced consultants enjoy providing on-site or off-site training classes for all major hardware verification languages and methodologies. See more
Our expertise also covers VIP qualification, formal verification, and SystemC modeling. See more
with
RELIABLE
TOOLS
Navigate right to find out more
about AMIQ EDA
Visit Website
AMIQ EDA provides software tools that enable design and verification engineers increase the speed and quality of new code development, simplify legacy code maintenance, accelerate language and methodology learning, and improve source code reliability.
AMIQ EDA was founded in 2008 and it has a team of ~35 RnD engineers. Our solutions have been adopted worldwide by 150+ companies in 35+ countries.
DVT Eclipse IDE / DVT IDE for VS Code
For design and verification engineers who are working with Verilog, SystemVerilog, VHDL, e Language, or PSS the Design and Verification Tools (DVT) Integrated Development Environment (IDE) significantly improves productivity. It is similar to well-known programming tools like Visual Studio and IntelliJ. See more
Verissimo SystemVerilog Testbench Linter
Verissimo is a static code analysis tool that allows engineers accurately identify SystemVerilog language pitfalls, semantic, style or performance issues, dead or duplicate code, and enforce compliance with verification methodologies like UVM or company specific code writing guidelines. See more
Specador Documentation Generator
Specador automatically generates accurate HTML documentation from SystemVerilog, Verilog, VHDL and e Language source code, based on effective compilation and comments analysis. It enables design and verification engineers to effortlessly generate and maintain proper and well-organized documentation. See more
DVT Debugger
The DVT Debugger is an extended capability of the DVT Eclipse IDE, which provides advanced debugging capabilities for the e language, SystemVerilog, Verilog and VHDL users and enables them to perform debugging from the same place where they develop their code, therefore, reducing debug flow complexity. See more
